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Display board & FPGA

I’ve been slowly porting the PJ5TTL cpu to VHDL, mostly so I can learn VHDL but also so I can have a “benchtop” version of the PJ5 for debugging external modules. The stumbling block was the divider, in the end Jon found a number of issues with my implementation and corrected them, so it’s now… More

Another video (Divide & display demo)

We’ve uploaded another video for PJ5 this time we’re demonstrating the hardware divide and alphanumeric display. This is the first time we’ve managed to put everything together and run with a complete set of boards on the CPU. Along the way we found a couple of interesting bugs; We’ve got the RS0/RS1 selection reversed, whoops… More

Progress & It’s been a while

It’s been a while since we posted anything, but we have been working away and we have some significant developments to share. First up we’ve managed to get the divider board working. This gives us an 8×8 hardware divide, which I think is unique amongst home built TTL processors. We did make one mistake with… More

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